Power Integrity of SiP (System in Package) Video
Joungho Kim
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Members: FreeEMC
IEEE Members: $29.95
Non-members: $39.95Length: 01:30:09
21 Jul 2010
In this talk, new modeling, design, and analysis approaches will be introduced with the consideration of power integrity. The unique methods are based on simultaneous and hierarchical chip-packaging, co-design and modeling in order to offer cost effective design solutions.
