The Whole Solution Space based Pin Pattern Optimization in BGA Technology

I/O pin counts have been able to increase significantly thanks to ball grid array (BGA) packages. The pogopin socket and elastomeric socket are developed to test BGA devices for quick device screening, device characterization and final production test. The cross talk issue introduced by using production test socket is inevitable due to the high density of speed I/Os. To mitigate the cross talk problem, this paper discusses the methodology to quickly generate pin patterns in a full solution space aiming to select the optimal pin patterns which will produce acceptable SI/PI performance in the chip design phase.